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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
Ver. 1.1 MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV -55HI, -70HI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
The M5M51008DFP,VP,RV,KV are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor (TFT) load cells and CMOS periphery result in a high density and low power static RAM. They are low standby current and low operation current and ideal for the battery back-up application. The M5M51008DVP,RV,KV are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD). Two types of devices are available. M5M51008DVP(normal lead bend type package), M5M51008DRV(reverse lead bend type package).Using both types of devices, it becomes very easy to design a printed circuit board.
PIN CONFIGURATION (TOP VIEW)
NC 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 DQ1 13 DQ2 14 DQ3 15 GND 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
ADDRESS INPUTS
FEATURES
Type name
M5M51008DFP,VP,RV,KV-55H M5M51008DFP,VP,RV,KV-70H
Access time (max)
Power supply current Active (1MHz) (max) stand-by (max)
DATA INPUTS/ OUTPUTS
VCC ADDRESS A15 INPUT CHIP SELECT S2 INPUT W WRITE CONTROL INPUT A13 A8 ADDRESS INPUTS A9 A11 OE OUTPUT ENABLE INPUT A10 ADDRESS INPUT S1 CHIP SELECT INPUT DQ8 DQ7 DQ6 DATA INPUTS/ DQ5 OUTPUTS DQ4
Outline 32P2M-A(FP)
A11 A9 A8 A13 W S2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26
55ns 70ns
15mA (1MHz)
40A (Vcc=5.5V)
Directly TTL compatible : All inputs and outputs Easy memory expansion and power down by S1,S2 Data hold on +2V power supply Three-state outputs : OR - tie capability OE prevents data contention in the I/O bus Common data I/O Package M5M51008DFP ************ 32pin 525mil SOP 2 M5M51008DVP,RV ************ 32pin 8 X 20 mm TSOP 2 M5M51008DKV ************ 32pin 8 X 13.4 mm TSOP
M5M51008DVP,KV
25 24 23 22 21 20 19 18 17
OE A10 S1 DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3
APPLICATION
Small capacity memory units A4 A5 A6 A7 A12 A14 A16 NC VCC A15 S2 W A13 A8 A9 A11
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Outline 32P3H-E(VP), 32P3K-B(KV)
17 18 19 20 21 22 23
M5M51008DRV
24 25 26 27 28 29 30 31 32
A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8 S1 A10 OE
Outline 32P3H-F(RV)
NC : NO CONNECTION
1
Ver. 1.1 MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV -55HI, -70HI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M51008D series are determined by a combination of the device control inputs S1,S2,W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W,S1 or S2,whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state(S1=L,S2=H). When setting S1 at a high level or S2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high- impedance state, allowing OR-tie with other chips and memory expansion by S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as ICC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the nonselected mode.
FUNCTION TABLE
S1 X H L L L S2 L X H H H W X X L H H Mode DQ OE X Non selection High-impedance X Non selection High-impedance Din X Write Dout L Read High-impedance H ICC Stand-by Stand-by Active Active Active
Note 1: "H" and "L" in this table mean VIH and VIL, respectively. 2: "X" in this table should be "H" or "L".
BLOCK DIAGRAM
* A3 9 17 18 15 14 13 12 11 10 7 * 21 22 13 DQ1 14 DQ2 15 DQ3 17 DQ4 18 DQ5 19 DQ6 20 DQ7 21 DQ8 DATA INPUTS/ OUTPUTS
A2 10 A5 A6 A7 A12 A14 7 6 5 4 3
131072 WORDS X 8 BITS (512 ROWS X128 COLUMNS X 16BLOCKS)
23 25 26 27 28 29
A16 2 A15 31
ADDRESS INPUTS A13 28 A8 27 A9 26 A11 25 4 3 2 1 5 A4 8 16 19 20 31 32 8 24 30 6 WRITE 29 W CONTROL INPUT 22 S1 30 S2 CHIP SELECT INPUTS
CLOCK GENERATOR
A1 11 A0 12 A10 23
OUTPUT 24 OE ENABLE INPUT 32 VCC 16 GND (0V)
* Pin numbers inside dotted line show those of TSOP
2
Ver. 1.1 MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV -55HI, -70HI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI VO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND Ta=25C Ratings - 0.3*~7 - 0.3*~Vcc + 0.3 0~Vcc 700 - 40~85 - 65~150 Unit V V V mW C C
* -3.0V in case of AC ( Pulse width 50ns )
DC ELECTRICAL CHARACTERISTICS (Ta= -40~85C, Vcc=5V10%, unless otherwise noted)
Symbol VIH VIL VOH VOL II IO Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Output current in off-state Active supply current (AC, MOS level) IOH= -1.0mA IOH= -0.1mA IOL=2mA VI=0~Vcc S1=VIH or S2=VIL or OE=VIH VI/O=0~VCC S1 0.2V, S2 VCC-0.2V other inputs 0.2V or VCC-0.2V Output-open(duty 100%) S1=VIL,S2=VIH, other inputs=VIH or VIL Output-open(duty 100%) 1) S2 0.2V, other inputs=0~VCC 2) S1 VCC-0.2V, S2 VCC-0.2V, other inputs=0~VCC S1=VIH or S2=VIL, other inputs=0~VCC 55ns 70ns 1MHz 55ns 70ns 1MHz ~25C ~40C -HI ~70C ~85C 39 34 4 42 37 5 Test conditions Min 2.2
-0.3*
Limits Typ
Max
Vcc + 0.3
Unit V V V V
0.8
2.4
Vcc - 0.5
0.4 1 1 80 70 15 85 70 15 2 6 20 40 3
V A A
ICC1
mA
ICC2
Active supply current (AC, TTL level)
mA
ICC3
Stand-by current
A
ICC4
Stand-by current
mA
* -3.0V in case of AC ( Pulse width 50ns )
CAPACITANCE (Ta= -40~85C, Vcc=5V10% unless otherwise noted)
Symbol CI CO Parameter Input capacitance Output capacitance FP,VP,RV,KV FP,VP,RV,KV Test conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz Min Limits Typ Max 8 10 Unit pF pF
Note 3: Direction for current flowing into an IC is positive (no mark). 4: Typical value is Vcc = 5V, Ta = 25C
3
Ver. 1.1 MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV -55HI, -70HI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta= -40~85C, 5V10% unless otherwise noted ) (1) MEASUREMENT CONDITIONS
Input pulse level ............... VIH=2.4V,VIL=0.6V (-70HI) VIH=3.0V,VIL=0.0V (-55HI) Input rise and fall time ...... 5ns Reference level ................ VOH=VOL=1.5V Output loads ..................... Fig.1, CL=100pF (-70HI) CL=30pF (-55HI) CL=5pF (for ten,tdis) Transition is measured 500mV from steady state voltage. (for ten,tdis)
VCC
1.8k DQ 990 CL ( Including scope and JIG )
Fig.1 Output load
(2) READ CYCLE
Limits Symbol tCR ta(A) ta(S1) ta(S2) ta(OE) tdis(S1) tdis(S2) tdis(OE) ten(S1) ten(S2) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select 1 access time Chip select 2 access time Output enable access time Output disable time after S1 high Output disable time after S2 low Output disable time after OE high Output enable time after S1 low Output enable time after S2 high Output enable time after OE low Data valid time after address -55HI Min Max 55 55 55 55 30 20 20 20 5 5 5 5 Min 70 -70HI Max 70 70 70 35 25 25 25 10 10 5 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns
(3) WRITE CYCLE
Symbol tCW tw(W) tsu(A) tsu(A-WH) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to W Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low Limits -55HI -70HI Min Max Min Max 55 70 45 50 0 0 50 55 50 55 50 55 25 30 0 0 0 0 20 25 20 25 5 5 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
4
Ver. 1.1 MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV -55HI, -70HI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS Read cycle
tCR A0~16 ta(A) tv (A)
ta (S1) S1
(Note 5) (Note 5)
tdis (S1)
S2
(Note 5)
ta (S2) ta (OE) ten (OE) tdis (S2)
(Note 5)
OE
(Note 5)
tdis (OE) ten (S1) ten (S2)
(Note 5)
DQ1~8
W = "H" level
DATA VALID
Write cycle (W control mode)
tCW
A0~16
tsu (S1) S1
(Note 5) (Note 5)
S2
(Note 5)
tsu (S2)
(Note 5)
tsu (A-WH) OE
tsu (A) W
tw (W)
trec (W)
tdis (W) tdis (OE) DQ1~8 ten (W) DATA IN STABLE tsu (D) th (D)
ten(OE)
5
Ver. 1.1 MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV -55HI, -70HI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Write cycle ( S1 control mode)
tCW A0~16
tsu (A)
tsu (S1)
trec (W)
S1
S2
(Note 5) (Note 7) (Note 5)
W
(Note 6) (Note 5) (Note 5)
tsu (D)
th (D)
DQ1~8
DATA IN STABLE
Write cycle (S2 control mode)
tCW A0~16
S1
(Note 5) (Note 5)
tsu (A) S2
tsu (S2)
trec (W)
(Note 7)
W
(Note 5)
(Note 6) (Note 5)
tsu (D)
th (D)
DQ1~8
DATA IN STABLE
Note 5: Hatching indicates the state is "don't care". 6: Writing is executed while S2 high overlaps S1 and W low. 7: When the falling edge of W is simultaneously or prior to the falling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. 8: Don't apply inverted phase signal externally when DQ pin is output mode.
6
Ver. 1.1 MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV -55HI, -70HI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS (Ta= -40~85C, unless otherwise noted)
Symbol VCC (PD) VI (S1) VI (S2) Parameter Power down supply voltage Chip select input S1 Chip select input S2 2.2VVcc(PD) 2VVcc(PD)2.2V 4.5VVcc(PD) Vcc(PD)<4.5V VCC = 3V 1) S2 0.2V, other inputs = 0~3V 2) S1 VCC-0.2V, S2 VCC-0.2V other inputs = 0~3V ~25C ~40C -HI ~70C ~85C Test conditions Min 2.0 2.2 Limits Typ Max Unit V
Vcc(PD)
V 0.8 0.2 1 3 10 20 A V
ICC (PD)
Power down supply current
(2) TIMING REQUIREMENTS (Ta= -40~85C, unless otherwise noted )
Symbol tsu (PD) trec (PD) Parameter Power down set up time Power down recovery time Test conditions Min 0 5 Limits Typ Max Unit ns ms
(3) POWER DOWN CHARACTERISTICS S1 control mode
VCC t su (PD) 4.5V 4.5V t rec (PD)
2.2V S1 S1 VCC - 0.2V
Note 9: On the power down mode by controlling S1,the input level of S2 must be S2 Vcc - 0.2V or S2 0.2V. The other pins(Address,I/O,WE,OE) can be in high impedance state.
2.2V
S2 control mode
VCC 4.5V 4.5V
S2
t su (PD)
t rec (PD)
0.2V S2 0.2V
0.2V
7
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